1. Field of the Invention
The field of the present invention relates to a nonvolatile semiconductor memory device and a manufacturing method therefor, and more particularly to an electrically programmable nonvolatile metal-oxide-semiconductor (MOS) memory device having an asymmetric source and drain and a manufacturing method therefor.
2. Description of Related Art
Flash memories are a growing class of nonvolatile storage integrated circuits. Flash memories have the capability of electrically erasing, programming, and reading a memory cell in the chip. A flash memory cell is formed using so-called floating gate transistors in which the data are stored in a cell by charging or discharging the floating gate. The floating gates are a conductive material, typically polysilicon, which is insulated from the channel of the transistor by a thin layer of oxide, or other insulating material. The floating gates are also insulated from the control gate/word-line of the transistor by a second layer of insulating material.
Data is stored in the memory cell by charging or discharging the floating gate. The floating gate is charged by either tunneling or injection of electrons through a thin dielectric separating the floating gate from the substrate. Fowler-Nordheim (FN) tunneling of electrons occurs when a large positive voltage is established between the floating gate and source or drain. The resultant high electric field imparts sufficient potential energy to electrons to allow them to surmount the energy barrier presented by the thin dielectric and tunnel into the floating gate. Alternatively, an injection mechanism may be used. Avalanche injection relies on an electric field of lesser magnitude than that required for FN tunneling. In avalanche injection, carrier-to-carrier collisions impart kinetic energy to electrons, which when coupled with the potential energy, is sufficient to allow them to surmount the energy barrier created by the thin dielectric. When the floating gate is charged, the threshold voltage for causing the memory cell channel to conduct is increased above the voltage applied to the word-line during a read operation. Thus, when a charged cell is addressed during a read operation, the cell does not conduct. The non-conducting state of the cell can be interpreted as a binary 1 or 0 depending on the polarity of the sensing circuitry.
The floating gate is discharged to establish the opposite memory state. This function is typically carried out by a FN tunneling mechanism between the floating gate and the source or the drain of the transistor, or between the floating gate and the substrate. For instance, the floating gate may be discharged through the source by establishing a large positive voltage from the source to the gate, while the drain is left at a floating potential.
Recently a second injection mechanism has been identified for use in programming of floating gate transistors. As set forth by Sakamoto et. al., A High Programming Throughput 0.35 um p-channel DINOR Flash Memory, VLSI Technology Digest, p.222, 1996, a band-to-band hot electron injection mechanism can be utilized for programming floating gates. Traditionally, band-to-band mechanisms have been associated with detrimental device characteristics such as: leakage current, word-line disturb and degradation of the insulating property of the tunneling oxide. These detrimental characteristics can be attributed to the attraction and trapping of hot holes (as opposed to hot electrons) in the thin dielectric during programming of n-channel devices. Holes are less mobile than electrons and more likely to get trapped in the dielectric. As Messrs. Sakamoto et. al., point out, it is only during programming of a n-channel device where negative voltages are applied to the control gate that hot holes are attracted to the floating gate. In a p-channel device, a positive programming voltage is applied to the control gate and hot holes are repelled from the floating gate and electrons are attracted. The cell utilized by Sakamoto et. al., is programmed by band-to-band hot electron injection (BBHE) and erased by channel FN tunneling. The symmetric cell structure is utilized in a Divided Nor (DINOR) architecture in which the source side of each column of memory cells is connected to a sub bit-line. The drain of each column of cells is connected to a separate bit-line from the source.
A trend in the industry to improve the packing density of a memory array, is to utilize a virtual ground architecture, rather than that disclosed by Messrs. Sakamoto et al. In a virtual ground architecture, the transistors of adjacent memory cell columns share a bit-line between the source and the drain of the transistors in adjacent columns. The need for a dedicated pair of bit-lines per column is eliminated. Any memory cell in the array can be programmed, or read by the application of appropriate voltages to the word-line and the bit-lines connected to it. In particular, the state of an addressed memory cell can be determined by sensing the current flowing through its source and drain by means of the bit lines connected thereto.
The major challenge of implementing a flash memory design utilizing a virtual ground architecture is to maintain disturb resistance. Disturb refers to the unacceptable alteration of the memory logic state on a cell sharing a bit-line and word-line with a cell being programmed or erased.
To realize further reductions in array size, it would be desirable to find a method for implementing BBHE in a virtual ground architecture.